Security

Administrator's password
Keyboard password (QuickLock)
HP iLO Management On System Management Chipset with:

SSL encryption
Secure Shell version 2
Advanced Encryption Standard (AES) and Triple Data Encryption Standard (3DES)
on browser, CLP and XML scripting interface
AES and RC4 encryption of video

External USB port enable/disable
Network server mode
Serial interface control
TPM (Trusted Platform Module) 1.2 option
Advanced Encryption Standard (AES)
Intel® Advanced Encryption Standard-New Instructions (AES-NI)
FIPS 140-2 Level-2 certification pending

Availability

Memory

Advanced ECC uses single device data correction (SDDC) to detect and correct single and
all multi-bit error that occurs within a single DRAM chip. Both x4 and x8 SDDC are
supported (x8 requires lockstep mode).
Memory online spare mode (also known as rank spare mode) detects a rank that is
degrading and switches operation to the spare rank.
Memory demand and patrol scrubbing to prevent accumulation of correctable errors and
reducing the likelihood of unplanned downtime.
Failed DIMM isolation improves the service time thus improving the overall system
availability.
Address parity protection available on RDIMMs and LRDIMMs detects address bit errors to
improve service time and overall system availability.

Mezzanine options and I/O

Support for one (1) FlexibleLOM, providing two (2) (i.e. redundant) Ethernet ports
Multiple mezzanine I/O expansion slots that support a wide variety of mezzanine cards
each supporting multiple data paths routed to redundant interconnect modules.
Network Adapter Teaming (bonding) provides network fault tolerance, transmit load
balancing, and switch-assisted load balancing.

Storage

Two (2) Small Form Factor hot-plug SAS/SATA HDD or SSD drive bays.
Choice of the HP Smart Array P244br Controller with 1GB FBWC/HP, Smart HBA H244br,
or the HP B140i (chipset SATA). RAID 0 and 1 support for all three storage controller
offerings.
Optional dual-port Fibre Channel mezzanine card(s) for redundant SAN connections.

Processor/Chipset

Processor internal sensors & thermal control protection against over-temperature
conditions.
Cache parity/ECC protects cache data from accidental data corruption.
Machine Check Architecture (MCA) detects and captures hardware errors such as system
bus, memory ECC, parity, and cache, and improves service time.
Intel® QPI Protocol Protection allows detection of data errors using a checksum of 8-bits.
Core Disable for FRB (fault resilient boot) allows a system to power-on despite a failing
core-pair. It uses BIST (built-in self-test) results to detect a failure and disables the target
core-pair upon subsequent boot.

QuickSpecs

HP ProLiant BL460c Generation 9 (Gen9) Server

Blade

Standard Features

DA - 15052   Worldwide QuickSpecs — Version 1 — 9.9.2014

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