Memory Subsystem
Architecture

Each Intel® Xeon® E5-2600v3 family processor socket contains four memory channels per
installed processor with three DIMMs per channel for a total of twelve (12) DIMMs or a grand total
of twenty-four (24) DIMMs for the server.

Memory Population
guidelines

General Memory Population Rules and Guidelines:

White DIMM slots denote the first slot of a channel. For 1 DPC (DIMM per channel) populate
white slots only.
A minimum of one DIMM is required per server.
Install DIMMs only if the corresponding processor is installed.
If only one processor is installed in a two processor system, only half of the DIMM slots are
available.
To maximize performance, it is recommended to balance the total memory capacity between
all installed processors and to load the channels similarly whenever possible.
When two processors are installed, balance the DIMMs across the two processors.
Populate DIMMs from heaviest load (quad-rank) to lightest load (single-rank) within a
channel. Heaviest load
(DIMM with most ranks) within a channel goes furthest from the processor.
RDIMMs operating at either 1.35V or 1.5V may be mixed in any order, but the system will
power them at the higher voltage.
Do not mix RDIMMs or LRDIMMs.
LRDIMMs are supported up to 3 DIMMs per channel.
Using the HP RBSU, 1.35V DIMMs can be changed to operate at 1.5V.
DIMMs of different speeds may be mixed in any order; the server will select a common

QuickSpecs

HP ProLiant DL380 Generation9 (Gen9)

Memory

DA - 15034   Worldwide QuickSpecs — Version 1 — 9.9.2014

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